This application claims priority to Korean Patent Application No. 2000-11821, filed on Mar. 9, 2000, and to No. 2000-55794, filed on Sep. 22, 2000, the contents of which are hereby incorporated herein by reference in their entireties.
The present invention relates to semiconductor manufacturing, and more particularly to methods of forming self-aligned contacts.
The semiconductor industry is continually striving to improve device performance while maintaining, or decreasing, the cost of the semiconductor product. These objects have been partially satisfied by the ability of the industry to create smaller semiconductor devices (or chips), thus enabling more semiconductor chips to be realized from a starting substrate, thus reducing the processing cost for a specific semiconductor chip. The ability to fabricate devices with sub-micron features has been the main contribution in obtaining smaller chips, with the smaller chips still maintaining levels of integration equal to integration levels achieved by larger chips.
The use of sub-micron features, or micro miniaturization, has resulted in smaller dimension of a gate electrode constituting a transistor. For example, feature sizes of about 0.1 microns may be realized. However, such micro-miniaturization may give rise to some problems in conventional gate electrode process. Particularly, micro-miniaturization may not ensure the reliability of the gate insulating layer.
A conventional gate electrode process is described as follows. A device isolation region is formed on a semiconductor substrate and impurities are implanted to form a channel region. A gate oxide layer and a gate electrode layer, such as polysilicon/tungsten layer, are sequentially formed and patterned into a gate electrode. Using the gate electrode as an implanting mask, impurities are implanted into the substrate to form low concentration drain regions, namely, LDD (lightly doped drain) regions.
The gate oxide may be subject to plasma damage during gate electrode patterning. In addition, the impurities implantation for the channel may degrade the reliability of the gate oxide. Furthermore, since channel impurities implantation is followed by LDD impurities implantation, impurities in the channel region may be re-distributed during an annealing process for curing point defects caused by the LDD impurities implantation.
In order to overcome some of the above-mentioned problems, a dummy gate process (or xe2x80x9cdamascene gate processxe2x80x9d) has been developed. FIGS. 1A, 1B and 2 are cross-sectional views of a semiconductor substrate to illustrate some problems associated with conventional dummy gate processes.
Referring to FIGS. 1A and 1B, a conventional dummy gate process is described. Referring now to FIG. 1A, a device isolation region 12 is formed in a predetermined portion of a semiconductor substrate 10. A dummy gate pattern (not shown) can be formed thereon. Using the dummy gate pattern as a mask, LDD impurities implantation can be carried out and annealed to form LDD region 16. A spacer 18 can be formed on a sidewall of the dummy gate pattern. A first insulating layer can be formed over an entire surface of the semiconductor substrate 10 and planarized down to a top surface of the dummy gate pattern to form a planarized first insulating layer 20. The dummy gate pattern can then be selectively removed to form a groove. Through the groove, impurities are implanted to form a channel region (not shown).
In turn, a gate electrode material can be deposited in the groove and on the first insulating layer 20, and then the gate electrode material can be planarized until the first insulating layer 20 is exposed, to form a gate electrode 24. Subsequently, a bit line and a storage node contact process can be carried out for electrical connection to the LDD region 16 outside of the gate electrode 24.
As is well known in the art, in order to provide process margin, a self-aligned contact process may be used during the bit line and storage node contact process. The self-aligned contact process selectively etches the oxide layer with respect to nitride layer covering the gate electrode, to form an opening exposing an LDD region. Accordingly, even in the presence of misalignment, the nitride layer protects the gate electrode, thereby blocking the gate electrode being exposed by the opening.
However, the conventional dummy gate process may suffer from problems during bit line and storage node contact formation processes. As shown in FIGS. 1A and 1B, the top of the gate electrode 24 may be exposed. Accordingly, the gate electrode 24 can be exposed when misalignment occurs during a photolithographic process used to form the contact. Namely, for a contact formation process, a second insulating layer 26 can be formed on the gate electrode 24 and on the first insulating layer 20. Through a photo-etching process, the second and first insulating layers 26 and 20 are selectively etched with respect to the nitride sidewall spacer 18, to form contact opening 28a and 28b. As can be seen, in the presence of the misalignment, the top of the gate electrode 24 can be exposed by the opening 28a and 28b, since the top of the gate is not protected. In addition, if the composition of the etchant is not optimal, the exposed gate electrode 24 may be etched. As a result, subsequently formed contact pads may come in contact with the gate electrode 24.
Accordingly, a protection nitride layer may be formed only on the gate electrode 24. However, it may be difficult to selectively form the protection nitride layer only on the gate electrode 24. As can be seen in FIG. 2, the protection nitride layer 25 can be formed on the first insulating layer 20 and the gate electrode 24. Accordingly, the protection nitride as well as the first and second insulating layers 20 and 26 is to be etched to form a contact opening, thereby making a self-aligned contact process difficult to achieve.
Embodiments according to the present invention can provide methods for forming self aligned contacts in integrated circuits. Pursuant to these embodiments, an insulating layer can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.
In some embodiments, the act of forming an insulating layer can be preceded by forming a dummy gate on the integrated circuit substrate including a spacer on a side wall of the dummy gate. In some embodiments, the act of forming the insulating later can be followed by removing the dummy gate and then forming a gate oxide layer in the groove.
In some embodiments, the act of removing can include dry etching the dummy gate and then wet etching the dummy gate. In some embodiments, the act of forming the conductive material in the groove can include the forming the conductive material in the groove recessed from an opening of the groove and on the insulating layer and removing the conductive material from the insulating layer and leaving conductive material in the groove.
In some embodiments, the act of removing the conductive material from the insulating layer and leaving conductive material in the groove can include forming an etching stopper layer on the conductive material in the groove and on the insulating layer and etching the etching stopper layer until the insulating layer is exposed.
In some embodiments the act of forming the conductive material in the groove can include forming the conductive material in the groove and on the insulating layer and etching the conductive material to recess the conductive material into the groove. In some embodiments, the act of etching the conductive material can include etching the conductive material to recess the conductive material about 2000 Angstroms from an opening of the groove. In some embodiments, an opening of the groove is wider than a base of the groove.
Further pursuant to embodiments of the present invention, a groove formed by removing a dummy gate pattern can be partially filled with a gate electrode material, and the remainder groove can be completely filled with a nitride layer to form a capping layer. Accordingly, a top portion of the damascene gate electrode can be covered with and protected by the capping layer.
Further according to the present invention, there are provided methods of forming a contact in a semiconductor substrate. The methods can include the acts of forming a dummy gate pattern on a semiconductor substrate, the dummy gate pattern having a sidewall spacer; forming a first insulating layer on an entire surface of the semiconductor substrate, the first insulating layer having a planar top surface and having the same level in height as the dummy gate pattern; selectively removing the dummy gate pattern with respect to the sidewall spacer and the first insulating layer to form a groove exposing a selected portion of the semiconductor substrate; forming a gate insulating layer on the exposed semiconductor substrate; partially filling the groove with a low resistant conductive material to form a gate electrode; and filling the remainder groove with an insulator having an etching selectivity with respect to the first insulating layer, to form a capping layer.
In some embodiments, the act of partially filling the groove with a low resistant conductive material to form a gate electrode comprises the acts of forming the low resistant conductive material in the groove and on the first insulating layer and selectively etching the low resistant conductive material with respect to the first insulating layer and the sidewall spacer as to be recessed to a selected depth from a top surface of the first insulating layer. Preferably, the low resistant conductive material is selected from a group consisting of titanium nitride/tungsten, polysilicon and polysilicon/silicide. Double layer of titanium nitride/tungsten is more preferable. In addition, a metal stable at high temperature can be used.
In other embodiments, the act of partially filling the groove with a low resistant conductive material to form a gate electrode comprises the act of forming the low resistant conductive material conformally in the groove and on the first insulating layer; forming an etching stopper on the conformal low resistant conductive material as to fill up the groove; etching the etching stopper and the conformal conductive material outside of the groove; and removing remainder etching stopper from the groove.
In other embodiments, the act of partially filling the groove with a low resistant conductive material to form a gate electrode comprises the acts of: forming the low resistant conductive material in the groove and on the first insulating layer to completely fill the groove; planarizing the conductive material until a top surface of the first insulating layer is exposed; and etching back the conductive material and recessing to a selected depth from a top surface of the insulating layer.
The act of forming a dummy gate pattern on a semiconductor substrate, the dummy gate pattern having a sidewall spacer, may comprise the acts of: forming a sacrificial insulating layer on the semiconductor substrate; forming a dummy gate material layer on the sacrificial insulating layer; patterning the dummy gate material layer to form the dummy gate pattern on the sacrificial insulating layer; forming a spacer layer on the sacrificial insulating layer and on the dummy gate pattern, the spacer layer having an etching selectivity with respect to the first insulating layer; and etching the spacer layer to form the sidewall spacer. Herein, the dummy gate pattern can be formed of a material that has an etching selectivity with respect to the spacer and the first insulating layer. For example, polysilicon and amorphous polysilicon can be used. In order to obtain an excellent dummy gate profile, polysilicon that is easily etched is more preferable. The sidewall spacer and the capping layer are formed of an insulator having an etching selectivity with respect to the first insulating layer. In addition, another spacer can be formed on inner sidewall of the groove to obtain sloped sidewall profile, resulting in relatively wider top portion as compared to bottom portion. Such sidewall profile of the groove can improve act coverage of the low resistant conductive material. Preferably, another sidewall spacer is formed of the same material as the sidewall spacer of the dummy gate pattern. Alternatively, the dummy gate pattern can be formed to have a sloped sidewall profile such that a top portion thereof is relatively wider than a bottom portion. Accordingly, the groove has a relatively wider top portion than the bottom.
The act of filling the remainder groove with an insulator having an etching selectivity with respect to the first insulating layer to form a capping layer can be followed by the acts of forming a second insulating layer on the first insulating layer and on the capping layer, the second insulating layer having an etching selectivity with respect to the sidewall spacer and the capping layer; patterning the second and first insulating layers to form an opening; removing exposed remainder sacrificial insulating layer to expose the substrate outside of the gate electrode; forming a conductive layer on the second insulating layer to fill the opening; and etching the conductive layer and the second insulating layer until the capping layer is exposed, to form a self-aligned contact pad. Preferably, the conductive layer is formed of the same material as the low resistant conductive material.
After forming the dummy gate pattern, LDD region can be further formed in the substrate outside of the dummy gate pattern by using the dummy gate pattern as a mask and first implanting impurities and annealing. At this time, the act of selectively removing the dummy gate pattern with respect to the sidewall spacer and the first insulating layer to form a groove exposing the semiconductor substrate comprise the acts of: selectively removing the dummy gate pattern with respect to the sidewall spacer, the first insulating layer and the sacrificial insulating layer; implanting second impurities into the exposed sacrificial insulating layer and annealing to form a self-aligned channel region in the substrate; and removing the exposed sacrificial insulating layer to expose the substrate.
The act of selectively removing the dummy gate pattern with respect to the sidewall spacer and the first insulating layer to form a groove exposing a selected portion of the semiconductor substrate can be followed by the acts of: removing the sidewall spacer and a part of the first insulating layer to enlarge the width of the groove, the enlarged groove having substantial vertical sidewall profile; and forming a reverse sidewall spacer on a sidewall of the enlarged groove, thereby narrowing a bottom of the resulting groove as compared to a top thereof. At this time, the sidewall spacer can be formed of the same material as the first insulating layer and the reverse sidewall spacer can be formed of a material that has an etching selectivity with respect to the first insulating layer.
Pursuant to other embodiments of the present invention, there are provided methods of forming a semiconductor device. The method can include the acts of forming a dummy gate pattern including a sacrificial insulating layer and a dummy gate material layer in this order on a semiconductor substrate; forming a sidewall spacer on sidewall of the dummy gate pattern; forming a first insulating layer on an entire surface of the semiconductor substrate, the first insulating layer having a planar top surface and having the same level in height as the dummy gate pattern; selectively removing the dummy gate pattern with respect to the sidewall spacer and the first insulating layer to form a groove exposing a selected portion of the semiconductor substrate; forming a gate oxide layer on the exposed semiconductor substrate; partially filling the groove with a low resistant conductive material to form a gate electrode; filling the remainder groove with an insulator having an etching selectivity with respect to the first insulating layer to form a capping layer; forming a second insulating layer on the first insulating layer and the capping layer, the second insulating layer having an etching selectivity with respect to the sidewall spacer and the capping layer; and selectively etching the second and first insulating layers with respect to the spacer and capping layer to form a self-aligned contact opening exposing the substrate outside of the gate electrode.
The act of partially filling the groove with a low resistant conductive material to form a gate electrode can include the acts of: forming the low resistant conductive material in the groove and on the first insulating layer to completely fill the groove; planarizing the conductive material until a top surface of the first insulating layer is exposed; and etching back the conductive material and recessing to a selected depth from a top surface of the insulating layer.
Pursuant to further embodiments according to the present invention, methods of forming semiconductor devices are provided. These embodiments can include forming a first dummy gate pattern and a second dummy gate pattern on a semiconductor substrate, wherein each dummy gate pattern has a sidewall spacer. The second dummy gate pattern can be wider than the first dummy gate pattern. A first insulating layer can be formed on an entire surface of the semiconductor substrate, wherein the first insulating layer has a planar top surface and has the same level in height as the dummy gate patterns. The first and second dummy gate patterns can be removed to form a first and a second grooves exposing selected portions of the substrate. First and a second gate oxide layers can be formed on the first and the second grooves respectively and a low resistance material layer can be formed on the first insulating layer thereby completely filling the first groove and partially filling the second groove due to width difference therebetween. An etching stopper can be formed on the conductive material to completely fill the remainder second groove. The etching stopper can be etched until the conductive material outside of the grooves is exposed. Using remainder etching stopper as an etch mask, the conductive material layer in the first groove can be etched to recess the conductive material from a top surface of the first insulating layer. An insulator can be formed to fill the first and second grooves to form a first capping layer and second capping layer.
The act of removing the first and second dummy gate patterns to form a first and a second grooves exposing a selected portion of the substrate can be followed by the acts of: removing the sidewall spacer and a portion of the first insulating layer on a top edge of the groove to enlarge the width of the grooves, the enlarged grooves having substantial vertical sidewall profile; and forming reverse sidewall spacers on a sidewall of the enlarged grooves, thereby narrowing a bottom of the resulting groove as compared to a top thereof. At this time, the sidewall spacer is formed of the same material as the first insulating layer and the reverse sidewall spacer is formed of a material that has an etching selectivity with respect to the first insulating layer.
In some embodiments according to the present invention, contacts can be formed by forming a second insulating layer on the first insulating layer and the capping layer, wherein the second insulating layer has an etching selectivity with respect to the sidewall spacer and the capping layer. The second and first insulating layers are selectively etched with respect to the spacer and capping layer to form a self-aligned contact opening exposing the substrate outside of the gate electrode. The first and second insulating layers can be silicon oxide and the capping layer and the sidewall spacer can be silicon nitride.
Preferably, each dummy gate pattern is formed of stacked layer including a sacrificial insulating layer and a dummy gate material layer. Herein, the act of forming a dummy gate pattern can be followed by a act of forming an LDD region in the substrate outside of the dummy gate pattern by using the dummy gate pattern as an implanting mask and implanting first impurities and annealing. In addition, the act of removing the dummy gate pattern to form a groove exposing the substrate comprises the acts of: selectively removing the dummy gate pattern with respect to the sidewall spacer, the first insulating layer and the sacrificial insulating layer; implanting second impurities into the exposed sacrificial insulating layer and annealing to form a self-aligned channel region in the substrate; and removing the exposed sacrificial insulating layer to expose the substrate.